Science News
Monolithic 3D integration of silicon transistors: a scalable process for vertically stacking ultrathin (≤10 nm) single-crystalline silicon layers enables multi-tiers of complementary junctionless transistors to be sequentially fabricated on the same starting…
💡 Researchers led by Qing Cao have developed a new method to stack high-performance silicon circuits directly and sequentially, a key step towards 3D chips that can boost computing power beyond current limits.
💡 This breakthrough addresses the "thermal budget" challenge, allowing new layers of silicon circuits to be built on top of existing ones at temperatures below 400°C, without damaging the underlying components.
💡 The new process uses ultrathin silicon nanomembranes and junctionless transistors, achieving high device performance and yields (98-100%) within the required temperature limits, paving the way for scalable industrial adoption.
#3DCodes #Semiconductor #TechInnovation
💡 This breakthrough addresses the "thermal budget" challenge, allowing new layers of silicon circuits to be built on top of existing ones at temperatures below 400°C, without damaging the underlying components.
💡 The new process uses ultrathin silicon nanomembranes and junctionless transistors, achieving high device performance and yields (98-100%) within the required temperature limits, paving the way for scalable industrial adoption.
#3DCodes #Semiconductor #TechInnovation
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