C/C++ Lint: Document its use and enforce it https://t.co/usPtEiu3aG #github #SystemVerilog #C++ #Python #Makefile #Filebench WML #Tcl #Forth
— first-issues (@first_issues) September 11, 2019
— first-issues (@first_issues) September 11, 2019
GitHub
C/C++ Lint: Document its use and enforce it · Issue #304 · lowRISC/ibex
#303 added a clang-format configuration to this repository to lint C/C++ code. We should Document our expectations on how developers run it, and possibly provide helper scripts for that. Run clang-...
Documentation: PMP documentation table rendering is broken https://t.co/Su7IBtUbOq #github #SystemVerilog #C++ #Python #Makefile #Filebench WML #Tcl #Forth
— first-issues (@first_issues) September 11, 2019
— first-issues (@first_issues) September 11, 2019
GitHub
Documentation: PMP documentation table rendering is broken · Issue #306 · lowRISC/ibex
This table isn't being rendered correctly:
[doc] `hwcfg` should not show the table header if no input/output exists in a IP https://t.co/Eni4trWT3w #github #SystemVerilog #Python #C #Smarty #Makefile #Shell #C++ #HTML #Emacs Lisp #CSS #Tcl #Meson #Filebench WML #Dockerfile #Stata #Assembly #Objective-C #Forth
— first-issues (@first_issues) November 5, 2019
— first-issues (@first_issues) November 5, 2019
GitHub
[doc] `hwcfg` should not show the table header if no input/output exists in a IP · Issue #878 · lowRISC/opentitan
Problem: If IP only has TL-UL port, `hwcfg` shows table header only. As seen in HMAC doc (could be changed after this issue is fixed), Peripheral Pins for Chip IO section shows no entry but only sh...
[doc/reggen] missing space in rendered register text https://t.co/mdYkQEY4kX #github #SystemVerilog #Python #C #Smarty #Makefile #Emacs Lisp #Shell #C++ #HTML #CSS #Tcl #Meson #Filebench WML #Dockerfile #Stata #Assembly #Objective-C #Forth
— first-issues (@first_issues) November 8, 2019
— first-issues (@first_issues) November 8, 2019
GitHub
[doc/reggen] missing space in rendered register text · Issue #942 · lowRISC/opentitan
The doc renderer for registers appends a "reset default" and "mask" value after the register text. This is done with a concatenation without spacing, so can rend...
Implement bit manipulation (B) RISC-V ISA extension https://t.co/90obtWc8vi #github #SystemVerilog #C++ #Python #Makefile #Filebench WML #Tcl #Forth
— first-issues (@first_issues) November 8, 2019
— first-issues (@first_issues) November 8, 2019
GitHub
Implement bit manipulation (B) RISC-V ISA extension · Issue #89 · lowRISC/ibex
The bit manipulation extension is currently being specified. Bit manipulation is a common task in many scenarios where Ibex could be used, so we should think about implementing this extension once ...
[util] Rename vendor_hw.py https://t.co/XGyU6rvJNl #github #SystemVerilog #Python #C #Smarty #Makefile #Emacs Lisp #HTML #CSS #Shell #C++ #Tcl #Meson #Filebench WML #Dockerfile #Stata #Assembly #Objective-C #Forth
— first-issues (@first_issues) November 15, 2019
— first-issues (@first_issues) November 15, 2019
GitHub
[util] Rename vendor_hw.py · Issue #607 · lowRISC/opentitan
The vendor_hw.py script was initially done (as the name says) to vendor in hardware components; it's now used for more than hardware, so we should rename it to a more appropriate name. Poss...
FPGA Optimizations https://t.co/IDIUuknOnV #github #SystemVerilog #C++ #Python #Makefile #Filebench WML #Shell #Tcl #Verilog #Forth
— first-issues (@first_issues) December 16, 2019
— first-issues (@first_issues) December 16, 2019
GitHub
FPGA Optimizations · Issue #522 · lowRISC/ibex
This issue for tracking different work items for optimizing Ibex for FPGA deployment. @ganoam will join us in January and as part of his Master thesis look into this. Things to investigate: Registe...
[verilator] Trace structs better https://t.co/BKFMMgzz1u #github #SystemVerilog #Python #C #Smarty #Makefile #Emacs Lisp #HTML #CSS #Shell #C++ #Meson #Tcl #Filebench WML #Assembly #Dockerfile #Stata #Objective-C #Forth
— first-issues (@first_issues) January 2, 2020
— first-issues (@first_issues) January 2, 2020
GitHub
[verilator] Trace structs better · Issue #1256 · lowRISC/opentitan
Looks like we can get much nicer signal traces in Verilator with --trace-structs passed to Verilator (change the top_earlgrey_*.core file for this.). If this works, we can most likely remove the bi...
[topgen/tlgen] Move simplify addr code to tlgen https://t.co/3pqMCdc9Pg #github #SystemVerilog #Python #C #Smarty #Makefile #Emacs Lisp #HTML #CSS #Shell #C++ #Meson #Tcl #Assembly #Filebench WML #Dockerfile #Stata #Objective-C #Forth
— first-issues (@first_issues) January 9, 2020
— first-issues (@first_issues) January 9, 2020
GitHub
[topgen/tlgen] Move simplify addr code to tlgen · Issue #1302 · lowRISC/opentitan
#1273 introduced the address merge feature. It is implemented in topgen while fabricating xbars. It makes more sense to move to tlgen as it can be done without top-level information nor the values ...
Ensure that relative operations handle broad API https://t.co/RxUHHuPWxD #github #C #Filebench WML #C++ #TeX #Python #Shell #Meson
— first-issues (@first_issues) May 29, 2020
— first-issues (@first_issues) May 29, 2020
GitHub
Ensure that relative operations handle broad API · Issue #7 · fsgeek/finesse
Quite a few calls have an absolute variant and a relative variant. In the absolute variant, the path is passed in and interpreted from root to branch. In the relative variant, the path is passed in...
Add logging to the Finesse API library https://t.co/khi2CYPaF2 #github #C #Filebench WML #C++ #TeX #Python #Shell #Meson
— first-issues (@first_issues) May 29, 2020
— first-issues (@first_issues) May 29, 2020
GitHub
Add logging to the Finesse API library · Issue #9 · fsgeek/finesse
The Finesse API has a transparent fallback model. It would be great if we had some way of tracing these, perhaps via environment variables, so that we can record when things fail. For example, if t...
Valid port range for game server containers as ENV https://t.co/fr1FpT42Hv #github #C #Filebench WML #C++ #TeX #Python #Shell #Meson #TypeScript #Dockerfile
— first-issues (@first_issues) May 29, 2020
— first-issues (@first_issues) May 29, 2020
GitHub
Valid port range for game server containers as ENV · Issue #3 · MysteryPoo/DD-Arena-MatchmakingServer
Port range is currently hard coded. Should be injectable through ENV variables. Good idea to map it to docker host as well when we support multiple docker hosts. That way each host can have its own...
Bitbucket: add hard link support https://t.co/ZLB3OYoOlZ #github #C #Filebench WML #C++ #TeX #Python #Shell #Meson #Jupyter Notebook
— first-issues (@first_issues) June 11, 2020
— first-issues (@first_issues) June 11, 2020
GitHub
Bitbucket: add hard link support · Issue #16 · fsgeek/finesse
Most of the support for this is already present. What's needed is: Add FUSE link call support Add test(s) for link counts Verify they work in the file system
Bitbucket: verify fsyncdir support https://t.co/0HSwJxJZUZ #github #JavaScript #HTML #CSS #C #Filebench WML #C++ #TeX #Python #Shell #Meson #Jupyter Notebook
— first-issues (@first_issues) June 11, 2020
— first-issues (@first_issues) June 11, 2020
GitHub
Bitbucket: verify fsyncdir support · Issue #17 · fsgeek/finesse
fsyncdir is implemented. Need to test and verify.
Bitbucket: forget_multi https://t.co/C7HGxWPWdl #github #C #Filebench WML #C++ #TeX #Python #Shell #Meson #Jupyter Notebook
— first-issues (@first_issues) June 11, 2020
— first-issues (@first_issues) June 11, 2020
GitHub
Bitbucket: forget_multi · Issue #18 · fsgeek/finesse
Forget is already coded and working. Forget_multi should be implemented as well; should be fairly easy given that this is just forget with a loop.
Cleanup: Remove REG_* defines from ibex_id_stage https://t.co/89P2px3u6F #github #SystemVerilog #Python #C++ #Makefile #Tcl #Filebench WML #Shell #Stata #Verilog #Forth #Emacs Lisp
— first-issues (@first_issues) June 17, 2020
— first-issues (@first_issues) June 17, 2020
GitHub
Cleanup: Remove REG_* defines from ibex_id_stage · Issue #30 · lowRISC/ibex
Can we get rid of those defines and replace them by parameters or structs?
Try out svlint https://t.co/DiewFwStKf #github #SystemVerilog #Python #Makefile #C++ #Tcl #Shell #Filebench WML #Stata #HTML #Verilog #Forth #Emacs Lisp
— first-issues (@first_issues) October 27, 2020
— first-issues (@first_issues) October 27, 2020
GitHub
Try out svlint · Issue #644 · lowRISC/ibex
I just found https://github.com/dalance/svlint and would be interested how it copes with the ibex code base.
Refactoring for the CV32E40X test-program definitions https://t.co/bWwDo9qKnV #github #Assembly #SystemVerilog #C #Makefile #Python #C++ #Tcl #Shell #Jinja #Filebench WML
— first-issues (@first_issues) Jan 12, 2022
— first-issues (@first_issues) Jan 12, 2022
GitHub
Refactoring for the CV32E40X test-program definitions · Issue #1107 · openhwgroup/core-v-verif
Task Outcome Removal of all deprecated toolchain selection parameters in the test-program definitions for the CV32E40X. Background information As documented in the toolchain selection sub-section o...