FST and real data type https://t.co/aYxrO7mn9d #github #VHDL #Ada #C #Python #Shell #C++ #Makefile #Verilog #Stata #Assembly #Batchfile #GDB #Coq
— first-issues (@first_issues) September 15, 2020
— first-issues (@first_issues) September 15, 2020
GitHub
FST and real data type · Issue #920 · ghdl/ghdl
When I use real variables or signals, and use FST as the output file format, GTKWave displays them as NaN. When I use VCD as the output file format, they are displayed correctly. Also, when the rea...
Increase code coverage https://t.co/I5E4kYhLyB #github #Python #C++ #VHDL #C #Makefile #Verilog #SystemVerilog #Coq #Dockerfile
— first-issues (@first_issues) September 18, 2020
— first-issues (@first_issues) September 18, 2020
GitHub
Increase code coverage · Issue #1962 · cocotb/cocotb
There are a few reasons why coverage is low; the reasons vary. This issue exists to list and track the completion of tasks relating to increasing code coverage. I think the next realistic goal is t...
Revisit CLI syntax https://t.co/jLp0cQjr5U #github #VHDL #Ada #C #Python #Shell #C++ #Makefile #Verilog #Stata #Assembly #Batchfile #GDB #Coq
— first-issues (@first_issues) September 21, 2020
— first-issues (@first_issues) September 21, 2020
GitHub
Revisit CLI syntax · Issue #1204 · ghdl/ghdl
Currently, the architecture of the CLI is based on (sub)commands and options. Commands are expected to be provided as the first argument, and do effectively decide which feature is to be used. OTOH...
Blood group- to be marked as mandatory https://t.co/hTgxrMQFDI #github #VHDL #Ada #C #Python #Shell #C++ #Makefile #Verilog #Stata #Assembly #Batchfile #GDB #Coq #TypeScript #JavaScript #SCSS #CSS #HTML #Reason #Dockerfile
— first-issues (@first_issues) September 21, 2020
— first-issues (@first_issues) September 21, 2020
GitHub
Blood group- to be marked as mandatory · Issue #652 · coronasafe/care_fe
Blood group in Basic Details form is actually a mandatory field. But its not marked as one. Please add an "*" to mark it as a mandatory field.
cuckoo_cam is a dcp built on xcvu9p-flga2104-2L-e https://t.co/ABfMTjRMZE #github #C# #HTML #C# #C++ #PowerShell #C #Tcl #SystemVerilog #Verilog #C #Coq #Makefile #VHDL #Shell
— first-issues (@first_issues) September 24, 2020
— first-issues (@first_issues) September 24, 2020
GitHub
cuckoo_cam is a dcp built on xcvu9p-flga2104-2L-e · Issue #3 · hpcn-uam/Limago
What is cuckoo_cam? It is a checkpoint built on xcvu9p-flga2104-2L-e now. Is it possible to build it to other cards? If it can also be generated by tcl or source RTLs that makes things more easier....
universalize debug target https://t.co/0qdeeF1eCN #github #Python #C++ #VHDL #C #Makefile #Verilog #SystemVerilog #Coq #Dockerfile
— first-issues (@first_issues) September 29, 2020
— first-issues (@first_issues) September 29, 2020
GitHub
universalize debug target · Issue #2016 · cocotb/cocotb
The debug target is seen in a couple simulator's makefiles (but not all), and only seems to run gdb. Now that we have COCOTB_ATTACH, running the simulator by calling gdb is unnecessary. How...
Address counter optimization https://t.co/PcZ2W4lSnF #github #VHDL
— first-issues (@first_issues) October 11, 2020
— first-issues (@first_issues) October 11, 2020
GitHub
Address counter optimization · Issue #11 · rftafas/stdcores
Must look for #8 Instead of adding data_word_size, figure how many addr_v bits will always be zero and keep adding just 1.
FIR - Unfolded - VHDL https://t.co/40aUTykm44 #github #JavaScript #HTML #CSS #SCSS #R #Verilog #VHDL #Roff #MATLAB #TeX #Shell #Tcl #C #Stata
— first-issues (@first_issues) October 20, 2020
— first-issues (@first_issues) October 20, 2020
Document how cocotb sets values on signals https://t.co/uw2PE24bg0 #github #Python #C++ #VHDL #C #Makefile #Verilog #SystemVerilog #Coq #Dockerfile
— first-issues (@first_issues) October 26, 2020
— first-issues (@first_issues) October 26, 2020
GitHub
Document how cocotb sets values on signals · Issue #2160 · cocotb/cocotb
Cocotb deposits values on signals. It does not behave like another driver. This should be made more explicit. And this is where the documentation for Force, Release, and Freeze should go, not in th...
Complaint progress bar in tutor exercise dashboard not the same as in tutor course dashboard https://t.co/aiM3JYQOQJ #github #Java #TypeScript #HTML #Scala #JavaScript #SCSS #Python #Shell #Assembly #Kotlin #Haskell #C #VHDL #Dockerfile
— first-issues (@first_issues) October 28, 2020
— first-issues (@first_issues) October 28, 2020
GitHub
Complaint progress bar in tutor exercise dashboard not the same as in tutor course dashboard · Issue #2124 · ls1intum/Artemis
Describe the bug The progress bar shows in the tutor course dashboard 0/1 complaints, which is correct as the complaint was recently created. In the tutor exercise dashboard the progress bar displa...
Remove output latch from SPI Slave on oversampled mode https://t.co/CrL3Cuq1gl #github #VHDL
— first-issues (@first_issues) October 28, 2020
— first-issues (@first_issues) October 28, 2020
GitHub
Remove output latch from SPI Slave on oversampled mode · Issue #20 · rftafas/stdcores
Native clock mode used an latch on output as means to give as much time as possible to AXI Bus to respond. Since oversampled mode has MCK>8*SPCK, probably this latch won't be necessa...
Add warning output to Fletchgen for unused metadata fields https://t.co/bh8KC6zUzZ #github #VHDL #C++ #Python #Tcl #C #CMake #Makefile #Shell
— first-issues (@first_issues) October 29, 2020
— first-issues (@first_issues) October 29, 2020
GitHub
Add warning output to Fletchgen for unused metadata fields · Issue #246 · abs-tudelft/fletcher
It would be helpful to have Fletchgen output warnings for unused metadata fields that start with fletcher_. For example, (this happened to me) when someone adds fletchgen_epc to Schema metadata ins...
Disable Override Assessment button when the assessment was not changed https://t.co/bjfa8ks5bZ #github #Java #TypeScript #HTML #SCSS #Scala #JavaScript #Python #Swift #Shell #OCaml #CSS #Assembly #Kotlin #Dockerfile #Haskell #VHDL #C
— first-issues (@first_issues) Jan 12, 2022
— first-issues (@first_issues) Jan 12, 2022
Twitter
first-issues
Disable Override Assessment button when the assessment was not changed github.com/ls1intum/Artem… #github #Java #TypeScript #HTML #SCSS #Scala #JavaScript #Python #Swift #Shell #OCaml #CSS #Assembly #Kotlin #Dockerfile #Haskell #VHDL #C
InvalidPasswords Exception is ambiguous https://t.co/ccnnXqsfHa #github #Python #Dockerfile #Java #TypeScript #HTML #SCSS #Scala #JavaScript #Python #Swift #Shell #OCaml #CSS #Assembly #Kotlin #Dockerfile #Haskell #VHDL #C
— First Issues Bot (@first_issues) Jan 22, 2022
— First Issues Bot (@first_issues) Jan 22, 2022
GitHub
InvalidPasswords Exception is ambiguous · Issue #4628 · ls1intum/Artemis
Not my exception, the naming is a bit ambiguous: This exception gets thrown if the provided password doesn't match the requirements (registration, etc.) Originally posted by @julian-christl...
Clear up all console.log in frontend https://t.co/bV7sYQ5W7J #github #Python #Dockerfile #Java #TypeScript #HTML #SCSS #Scala #JavaScript #Python #Swift #Shell #OCaml #CSS #Assembly #Kotlin #Dockerfile #Haskell #VHDL #C #TypeScript #Go #JavaScript #Shell #HTML #CSS #Docke…
— First Issues Bot (@first_issues) Jan 22, 2022
— First Issues Bot (@first_issues) Jan 22, 2022
GitHub
Clear up all console.log in frontend · Issue #26 · Fellowmark/fellowmark
console.log causes vulnerability issues. Lets discuss whether we should remove it or not?
document configuring logger to separate simulator and cocotb logs https://t.co/7BszvsPWze #github #Python #C++ #VHDL #C #Makefile #Verilog #SystemVerilog #PowerShell
— First Issues Bot (@first_issues) Jan 22, 2022
— First Issues Bot (@first_issues) Jan 22, 2022
GitHub
document configuring logger to separate simulator and cocotb logs · Issue #2835 · cocotb/cocotb
#23 was closed, and a follow on action was to document how to configure the cocotb logger to separate it and the simulator stdout.
Links to all Complaints and More Feedback Requests in Assessment Dashboard for Instructors missing https://t.co/V0bnsd8PCC #github #Java #TypeScript #HTML #SCSS #Scala #JavaScript #Python #Swift #Shell #OCaml #CSS #Assembly #Kotlin #Dockerfile #Haskell #VHDL #C
— First Issues Bot (@first_issues) Jan 27, 2022
— First Issues Bot (@first_issues) Jan 27, 2022
GitHub
Links to all Complaints and More Feedback Requests in Assessment Dashboard for Instructors missing · Issue #4613 · ls1intum/Artemis
Describe the bug Since recently, we noticed that the links to all Complaints and all More Feedback Requests are missing in the Assessment Dashboard. https://artemis.ase.in.tum.de/course-management/...
Exam Mode: Evaluating quizzes an assessing unsubmitted exams trigger loading animation for both buttons https://t.co/pBGToruvkm #github #Java #TypeScript #HTML #SCSS #Scala #JavaScript #Python #Swift #Shell #OCaml #CSS #Assembly #Kotlin #Dockerfile #Haskell #VHDL #C #Java…
— First Issues Bot (@first_issues) Jan 27, 2022
— First Issues Bot (@first_issues) Jan 27, 2022
GitHub
Exam Mode: Evaluating quizzes an assessing unsubmitted exams trigger loading animation for both buttons · Issue #4620 · ls1intum/Artemis
Describe the bug When, as an instructor, you either trigger the evaluation of quizzes or the assessment of resubmitted exams on the exam assessment dashboard, the loading animation is shown for bot...
Evaluator doesn't reduce some self comparisons https://t.co/BTJm50U1Lb #github #Bluespec #Haskell #Emacs Lisp #Verilog #VHDL #SystemVerilog #C++ #Makefile #Tcl #C #Shell #SuperCollider #HTML #Perl #Vim script #Batchfile #Smalltalk #Roff #Python #Dockerfile #sed
— First Issues Bot (@first_issues) Mar 4, 2022
— First Issues Bot (@first_issues) Mar 4, 2022
GitHub
Evaluator doesn't reduce some self comparisons · Issue #460 · B-Lang-org/bsc
The evaluator is able to reduce rg == rg and rg != rg (to True and False), but doesn't reduce expressions with <, <=, >, or >=. This can be seen in the following...
Add resets to all register state https://t.co/SaWTE96r2E #github #Verilog #VHDL #C #Assembly #Makefile #Python #C++ #Shell #Rust
— First Issues Bot (@first_issues) Mar 16, 2022
— First Issues Bot (@first_issues) Mar 16, 2022
GitHub
Add resets to all register state · Issue #359 · antonblanchard/microwatt
Currently we don't reset registers or we use := initalisers when defining signals. This works ok in FPGAs and ghdl sim but sucks for ASIC and gate level sim as it causes a lot of X state pr...