pip install tapa issue https://t.co/P1UWKQ1upW #github #C #C++ #Python #Verilog #CMake #Shell #Roff #Tcl
— First Issues Bot (@first_issues) Feb 25, 2022
— First Issues Bot (@first_issues) Feb 25, 2022
GitHub
pip install tapa issue · Issue #23 · UCLA-VAST/tapa
python3 -m pip install --editable tapa/backend/python => succeed python3 -m pip install tapa/backend/python => fail FileNotFoundError: [Errno 2] No such file or directory: '/t...
Error TS2339 해결 https://t.co/UAXkTadWij #github #C #C++ #Python #Verilog #CMake #Shell #Roff #Tcl #TypeScript #CSS #JavaScript #HTML
— First Issues Bot (@first_issues) Feb 25, 2022
— First Issues Bot (@first_issues) Feb 25, 2022
GitHub
Error TS2339 해결 · Issue #7 · zzoin/zzoin-frontend
TS2339: Property 'height' does not exist on type 'ThemedStyledProps<Pick<DetailedHTMLProps<ButtonHTMLAttributes, HTMLButtonElement>, "ke...
Install error Pynq 2.7 https://t.co/2srSxObqAK #github #Java #Tcl #Jupyter Notebook #Python #Verilog #C++ #Makefile
— First Issues Bot (@first_issues) Mar 1, 2022
— First Issues Bot (@first_issues) Mar 1, 2022
GitHub
Install error Pynq 2.7 · Issue #58 · Xilinx/PYNQ_Composable_Pipeline
Trying to install Pynq-Composable_Pipeline on Pynq-Z1 with version 2.7 The command sudo pip3 install PYNQ_Composable_Pipeline/ --verbose returns the following. I checked Cython version, I have the ...
Incorrect path to https://t.co/BXWOWB5Usa in mio3.yaml https://t.co/bDODX8JtLe #github #Python #Verilog #SystemVerilog #Tcl
— First Issues Bot (@first_issues) Mar 1, 2022
— First Issues Bot (@first_issues) Mar 1, 2022
Evaluator doesn't reduce some self comparisons https://t.co/BTJm50U1Lb #github #Bluespec #Haskell #Emacs Lisp #Verilog #VHDL #SystemVerilog #C++ #Makefile #Tcl #C #Shell #SuperCollider #HTML #Perl #Vim script #Batchfile #Smalltalk #Roff #Python #Dockerfile #sed
— First Issues Bot (@first_issues) Mar 4, 2022
— First Issues Bot (@first_issues) Mar 4, 2022
GitHub
Evaluator doesn't reduce some self comparisons · Issue #460 · B-Lang-org/bsc
The evaluator is able to reduce rg == rg and rg != rg (to True and False), but doesn't reduce expressions with <, <=, >, or >=. This can be seen in the following...
RISC V Core program https://t.co/BAW1KiEV3x #github #Verilog
— First Issues Bot (@first_issues) Mar 4, 2022
— First Issues Bot (@first_issues) Mar 4, 2022
GitHub
RISC V Core program · Issue #2 · SeedVGP/DLPR32
Create the Processor having three pipeline
Add icons to extensions https://t.co/JAb7SLwUsZ #github #Verilog #TypeScript #JavaScript #Shell
— First Issues Bot (@first_issues) Mar 4, 2022
— First Issues Bot (@first_issues) Mar 4, 2022
GitHub
Add icons to extensions · Issue #136 · Divlo/vscode-styled-jsx
Description Add a vercel icon to the two extensions. Describe the solution you'd like create an assets directory add an icon file there add an icon property in package.json Describe alterna...
Divider: missing vertical relation between `Do` instruction and `Endpoint` https://t.co/D5v6pChYls #github #Haskell #Verilog #TypeScript #Stata #Makefile #HTML #SCSS #Dhall
— First Issues Bot (@first_issues) Mar 7, 2022
— First Issues Bot (@first_issues) Mar 7, 2022
GitHub
Divider: missing vertical relation between `Do` instruction and `Endpoint` · Issue #205 · ryukzak/nitta
Divider, missing vertical relation between Do instruction and Endpoint. Current state: this error was filtering out during the integrity check. See TODO in NITTA.Model.ProcessIntegrity. How to fix ...
Add CAD steps and refactoring to IntegretyCheck of ProcessUnits https://t.co/6yNIgTIB7e #github #Haskell #Verilog #TypeScript #Stata #Makefile #HTML #SCSS #Dhall
— First Issues Bot (@first_issues) Mar 7, 2022
— First Issues Bot (@first_issues) Mar 7, 2022
GitHub
Add CADStep + RefactorStep to IntegretyCheck of ProcessUnits · Issue #207 · ryukzak/nitta
Currently, we check relations: [ checkVerticalRelations (up2down pu) (pid2intermediate pu) (pid2endpoint pu) "intermediate not related to endpoint" , checkVerticalRelations (down2...
Inconsistency with Decoupled and DecoupledIO https://t.co/4iIpH5Pg4u #github #Scala #Makefile #C++ #Verilog
— First Issues Bot (@first_issues) Mar 7, 2022
— First Issues Bot (@first_issues) Mar 7, 2022
GitHub
Inconsistency with Decoupled and DecoupledIO · Issue #2436 · chipsalliance/chisel3
It's a source of confusion when to use Decoupled and when to use DecoupledIO -- can we just make them the same name and deprecate the inconsistent name? Type of issue: feature request Impac...
ModuleNotFoundError: No module named 'pynq_composable.overlay' https://t.co/uWVeTwYHkA #github #Tcl #Jupyter Notebook #Python #Verilog #C++ #Makefile
— First Issues Bot (@first_issues) Mar 12, 2022
— First Issues Bot (@first_issues) Mar 12, 2022
GitHub
ModuleNotFoundError: No module named `pynq_composable.overlay` · Issue #70 · Xilinx/PYNQ_Composable_Pipeline
When the pynq_composable package is installed in a board that is not supported by the composable video overlay, the pynq_composable.overlay is register as a module, however the /usr/local/share/pyn...
Hide "each" amount when there's only one recipient https://t.co/vlEPyP2vUb #github #Tcl #Jupyter Notebook #Python #Verilog #C++ #Makefile #Python #HTML #CSS #JavaScript #Jinja #Makefile #Dockerfile #Shell #Mako
— First Issues Bot (@first_issues) Mar 12, 2022
— First Issues Bot (@first_issues) Mar 12, 2022
GitHub
Hide "each" amount when there's only one recipient · Issue #1002 · spiral-project/ihatemoney
When there's only one person in the For whom? column (this is the case for the slight majority of my transactions), the How much? column is unnecessarily cluttered, with the same value alwa...
Initial Work on the GUI Elements https://t.co/yyEceZ8Svd #github #Tcl #Jupyter Notebook #Python #Verilog #C++ #Makefile #Python #HTML #CSS #JavaScript #Jinja #Makefile #Dockerfile #Shell #Mako #Python #Shell
— First Issues Bot (@first_issues) Mar 12, 2022
— First Issues Bot (@first_issues) Mar 12, 2022
GitHub
Initial Work on the GUI Elements · Issue #24 · andrewk10/AutoCompliance
Is your feature request related to a problem? Please describe. The GUI for AutoCompliance needs to be created. Describe the solution you'd like A functional GUI which can call the underlyin...
A dialect for scheduling problems https://t.co/w3BAbKPRsk #github #C++ #MLIR #Python #CMake #C #Verilog #Shell #SystemVerilog #Cap'n Proto #PowerShell #Tcl
— First Issues Bot (@first_issues) Mar 13, 2022
— First Issues Bot (@first_issues) Mar 13, 2022
GitHub
A dialect for scheduling problems · Issue #2760 · llvm/circt
@mikeurbach and I think it would be useful to have an import/export format for scheduling problem instances, e.g. for writing test cases and benchmarking independent from the concrete (and potentia...
[wish] [ssreflect] nicer "duplicate clear" warning https://t.co/jKsykz6MgS #github #OCaml #Coq #TeX #Shell #Standard ML #C #Python #Makefile #Nix #Emacs Lisp #CSS #Dockerfile #JavaScript #Batchfile #sed #V #Verilog
— First Issues Bot (@first_issues) Mar 14, 2022
— First Issues Bot (@first_issues) Mar 14, 2022
GitHub
[wish] [ssreflect] nicer "duplicate clear" warning · Issue #15803 · coq/coq
Code like have {H}H : ... triggers a cryptic warning. It should suggest to write have {}H : ... instead. See also: https://coq.zulipchat.com/#narrow/stream/237664-math-comp-users/topic/duplicate.20...
PYNQ-Z2 Compiler with Vivado GUI https://t.co/yFxGojbjo9 #github #Tcl #Jupyter Notebook #Python #Verilog #C++ #Makefile
— First Issues Bot (@first_issues) Mar 15, 2022
— First Issues Bot (@first_issues) Mar 15, 2022
GitHub
PYNQ-Z2 Compiler with Vivado GUI · Issue #71 · Xilinx/PYNQ_Composable_Pipeline
Sorry to one question. Built the vivado project for PYNQ-Z2 board by below command successfully: cd PYNQ_Composable_Pipeline/boards/Pynq-Z2 make project When I trying change the static ip : ex: col...
Generating Docs Page Not Found https://t.co/bVicY0onle #github #Tcl #Jupyter Notebook #Python #Verilog #C++ #Makefile #Python
— First Issues Bot (@first_issues) Mar 15, 2022
— First Issues Bot (@first_issues) Mar 15, 2022
GitHub
Generating Docs Page Not Found · Issue #131 · airctic/icedata
📓 Documentation Update Clicking on the Contributing Guide link from the side-bar on https://airctic.github.io/icedata/ directs to https://airctic.github.io/icedata/readme.md The body of the page di...
Add test for MissingSecretKeyException https://t.co/4CqIaAsS2f #github #Tcl #Jupyter Notebook #Python #Verilog #C++ #Makefile #Python #Java #Shell
— First Issues Bot (@first_issues) Mar 15, 2022
— First Issues Bot (@first_issues) Mar 15, 2022
GitHub
Add test for MissingSecretKeyException · Issue #262 · pgpainless/pgpainless
Add a test for what happens if a key is used for signing, but the signing secret key is missing.
Add resets to all register state https://t.co/SaWTE96r2E #github #Verilog #VHDL #C #Assembly #Makefile #Python #C++ #Shell #Rust
— First Issues Bot (@first_issues) Mar 16, 2022
— First Issues Bot (@first_issues) Mar 16, 2022
GitHub
Add resets to all register state · Issue #359 · antonblanchard/microwatt
Currently we don't reset registers or we use := initalisers when defining signals. This works ok in FPGAs and ghdl sim but sucks for ASIC and gate level sim as it causes a lot of X state pr...